1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a flash memory device and a method of making thereof.
2. Background of the Related Art
In general, a flash memory is an electrically erasable nonvolatile memory. FIGS. 1a and 1b are cross-sectional views of a general flash memory cell for illustrating writing and erasing operations. Initially, when applying a voltage to a control gate and a drain (V.sub.CG &gt;V.sub.D, V.sub.D .noteq.0), no electrons exist in a floating gate. Electrons are attracted to a channel region between source and drain, so that a current begins to flow.
During programming, a hot electron injection method such is used for a conventional UV light erasing type electrically programmable read only memory (EPROM). As shown in FIG. 1a, a high voltage is applied to a control gate 25 in order to inject electrons created near a drain 28 of the memory cell into a floating gate 23. Accordingly, if electrons over a specified amount are injected into floating gate 23, a threshold voltage (Vth) of a memory cell transistor is raised. A high energy barrier is created to maintain a state where the electrons are accumulated in floating gate 23. Due to a difference of threshold voltages between an electron accumulated memory cell transistor and a memory cell transistor, in which no electron is injected, an information of "0" or "1" is distinguished.
In order for the information to be erased, the electrons accumulated in floating gate 23 are removed by Fowler Nordheim type tunneling current, and the threshold voltage of the memory cell transistor returns to the initial value. As shown in FIG. 1b, if a high voltage is applied to a source 27, the electrons accumulated in floating gate 23 are discharged to source 27 by Fowler Nordheim type tunneling mechanism through a part of a thin oxide film 22, where the source junction and floating gate 23 overlap with each other. The electrons of the floating gate are discharged to leave a positive (+) charge in the floating gate. Thus, the threshold voltage is lowered and the current flows smoothly in the channel region.
FIGS. 2a to 2f are cross-sectional views for illustrating a method of manufacturing the conventional flash memory. Initially, a tunneling oxide film 22 is deposited on a P-type silicon substrate 21 (FIG. 2a). Thereafter, a first polysilicon layer 23 is formed on a tunneling oxide film 22 (FIG. 2b). An interpoly dielectric layer 24 is formed on first polysilicon layer 23 (FIG. 2c), and a second polysilicon layer 25 is formed on interpoly dielectric layer 24 FIG. 2d).
A photoresist 26 is coated on second polysilicon layer 25 for the control gate and patterned by exposure and development process, as shown in FIG. 2e. Using patterned photoresist 26 as a mask, second polysilicon layer 25, interpoly dielectric layer 24, first polysilicon layer 23 and tunneling oxide film 22 are removed selectively to form the floating and control gates and the gate oxides. See FIG. 2f. Using second polysilicon layer 25 of the control gate as a mask, an impurity ion implantation is carried out to form source/drain impurity diffusion regions 27 and 28.
Programming of such flash memory is accomplished by injecting hot electrons created in the channel into floating gate 25. At this time, a ratio of a voltage applied to the floating gate with respect to a voltage applied to the control gate in order to form the channel is known as a coupling ratio. As such a coupling ratio becomes larger, the programming efficiency is increased.
To erase or discharge the electrons accumulated in the floating gate through Fowler Nordheim type tunneling mechanism, a positive (+) voltage is applied to source 27 of the deep junction. In order to improve the erasing efficiency, the thickness of tunneling oxide film 22 under floating gate 23 is made thin, and floating gate 23 and control gate 25 are formed of an N-type polysilicon. If a high voltage is applied to source 27 for the erasing operation, the energy band of tunneling oxide film 22 has a steep slope. Accordingly, the tunneling of electrons are attained through the thinned energy barrier part of tunneling oxide film 22 to realize the erasing operation.
However, the above conventional flash memory cell transistor has various problems. For example, during the writing operation, tunneling oxide film 22 is degraded due to hot electrons, thereby deteriorating the reliability. Further, in order to raise the erasing efficiency, the oxide film of the floating gate is utilized as the tunneling oxide film, thereby decreasing the writing efficiency. Moreover, an application of a high voltage is necessary to create the hot electron carriers.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.